ASCH-PUF: A “Zero” Bit Error Rate CMOS Physically Unclonable Function With Dual-Mode Low-Cost Stabilization


Physically unclonable functions (PUF) have emerged as a promising solution for secure and low-cost key storage and hardware authentication. A key challenge in PUF designs is ensuring the reliability, or reproducibility of PUF keys under environmental variations. While error correction codes (ECC) could help achieve 100% reliable key, the overhead of the design grows with the worst-case bit-error rate (BER), which will become intractable in mass production (Fig. 36.5.1). Thus, physically more reliable PUF designs are highly desired to alleviate the burden on ECC. State-of-the-art PUF circuit topologies could reduce the native BER to less than 0.5%, but have not shown the potential for another order of magnitude BER reduction. Meanwhile, temporal/spatial majority voting and burn-in are common physical stabilization methods, but with limited efficacy. Dark (unstable) bit masking, on the other hand, has shown great potential to suppress BER before ECC. Finding potential dark bits across the full operating range is nontrivial. Extensive testing across temperatures is expensive and does not completely remove error bits when the evaluations is insufficient . Recently, a few dark bit detection techniques at nominal conditions were proposed. By perturbing a PUF cell in opposite directions, cells with small native mismatch and high flip probability can be identified. Sweeping body biasing has no area overhead and improves BER by 98%, but suffers from low detection accuracy and thus a large number of falsely discarded cells. The latest capacitive tilting in SRAM PUFs and ground resistance insertion in EE SRAM PUFs could detect all unstable bits in the experiments, but still suffer from low detection accuracy.

IEEE Journal of Solid-State Circuits (JSSC)
Yan He
Ph.D. Student (started in 2018)
Dai Li
PhD 2021, now at Google
Zhanghao Yu
PhD 2023, now at Intel
Kaiyuan Yang
Associate Professor of ECE