25.3 A 65nm Edge-Chasing Quantizer-Based Digital LDO Featuring 4.58ps-FoM and Side-Channel-Attack Resistance

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Low-Dropout Regulators (LDOs) are commonly desired for fine-grained power management in SoCs because of their compact area, high current efficiency, and small output ripple. Digital LDOs (DLDOs) are increasingly adopted in recent years thanks to voltage and process scalability. However, achieving a fast response to a load change requires a conventional synchronous DLDO to either increase its sampling frequency with a large power overhead, or include a large output capacitor $(mathrmC_mathrmOUT)$ with increased chip area and cost. Various control schemes have been proposed to mitigate these drawbacks. In synchronous designs, attempts have been made to employ more complex control algorithms to achieve faster response [1], and to replace the PMOS switch array with switched capacitors for reduced dynamic energy consumption [2]. On the other hand, asynchronous DLDOs with event-driven [3] and beat-frequency VCO-based structures [4] show promise across the key performance, power and area metrics. Recently, voltage regulators are also found to be useful in enhancing the resistance of cryptographic engines and processors against power and EM side-channel attacks (SCAs) [5]–[7], which are physical attacks representing a severe threat to mobile and embedded devices. Employing regulators for SCA defense is promising because they are already used in most systems and require no modifications to existing computing architectures and algorithms like other circuit-level defenses [8]–[9]. In this paper, we present a high-performance and SCA-aware DLDO leveraging the unique properties of the Edge-Chasing Quantizer (ECQ). The 65nm DLDO prototype achieves: 1) a 101.7mV droop and 506ns settling time after a 20mA, 0.1ns step load change, with only a 0.1nF capacitor; 2) a 0.018mm2 active area and 99.4% peak current efficiency; and, 3) more than 14000× improvement in power SCA resistance on a 128b AES engine, with 27.5% area, 19.4% power, and 4.54% performance overheads over a standalone AES, and negligible overhead when compared to an AES design integrated with conventional DLDOs.

2020 IEEE International Solid- State Circuits Conference - (ISSCC)
Yan He
Ph.D. Student (started in 2018)
Kaiyuan Yang
Assistant Professor of ECE