A 114-pW PMOS-Only, Trim-Free Voltage Reference with 0.26% within-Wafer Inaccuracy for nW Systems

Abstract

A sub-nW voltage reference is presented that uses only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation for LDOs and other applications in nW microsystems. Sixty chips from 3 different wafers in 180nm CMOS are measured, showing an untrimmed within-wafer $σ$/$μ$ of 0.26% and wafer-to-wafer $σ$/$μ$ of 1.9%. Measurement results also show a temperature coefficient of 48–124ppm/°C from -40°C to 85°C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114pW at 25°C.

Kaiyuan Yang

Associate Professor of ECE