A robust −40 to 120°C all-digital true random number generator in 40nm CMOS


An all-digital True Random Number Generator (TRNG) harvesting entropy from the collapse of 2 edges injected into one even-stage ring is fabricated in 40nm CMOS. A configurable ring and tuning loop provides robustness across a wide range of temperature (-40 to 120°C), voltage (0.6 to 0.9V), process variation, and external attack. The dynamic tuning loop automatically configures the ring to meet a sufficient collapse time, thereby maximizing entropy. All dies pass all NIST randomness tests across all measured operating conditions and power supply attacks. The all-digital TRNG occupies only 836μm2 and consumes 23pJ/bit at nominal 0.9V and 11pJ/bit at 0.6V.

2015 Symposium on VLSI Circuits (VLSI Circuits)
Kaiyuan Yang
Assistant Professor of ECE