An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations


This paper presents an all-digital true random number generator (TRNG) harvesting entropy from the collapse of two edges injected into one even-stage ring, fabricated in 40 and 180 nm CMOS technologies. A configurable ring and tuning loop provides robustness across a wide range of temperature ($-40,ĉirctextC$ to 120 °C), voltage (0.6 to 0.9 V), process variation, and external attack. The dynamic tuning loop automatically configures the ring to meet a sufficient collapse time, thereby maximizing entropy. Measured random bits pass all NIST randomness tests across all measured operating conditions and power supply attacks. In 40 nm, the TRNG occupies only $836,upmu textm̂$ and consumes 23 pJ/bit at nominal 0.9 V and 11 pJ/bit at 0.6 V.

IEEE Journal of Solid-State Circuits
Kaiyuan Yang
Assistant Professor of ECE