This work presents a PUF cell based on a simple sub-threshold 2-transistor (2T) amplifier implemented in 180nm CMOS featuring: (1) a small 553F2 PUF cell, integrated in an array with all peripheral circuits; (2) excellent stability: 1.65% native unstable bits, reaching 0.05% unstable bits with 11b temporal majority voting (TMV), and 3.16% and 2.01% flipping bits across wide temperature (-40120°C) and voltage (0.8-1.8V) ranges; (3) high energy efficiency of 11.3fJ/b at nominal 1.2V and 1.5fJ/b at 0.8V; (4) high throughput (4.8Gb/s) via highly parallel operation, despite using an older technology. A masking technique using body bias is employed to find unstable bits without costly temperature sweeps.