MePLER: A 20.6-pJ Side-Channel-Aware In-Memory CDT Sampler

Abstract

This work presents a MePLER, an in-Memory cumulative distribution table (CDT) sampler, featuring custom cell derived from NAND-Type CAM for range-matching, pipelined and segmented array for reduced energy, and suppressed timing and power side-channel leakage. The precision and sample range are configurable for different sampling requirements. A 65nm prototype achieves constant 85.9-MSps, 1-sample/cycle throughput, 20.6-pJ/sample efficiency, and 0.03-mm2 footprint.

Publication
2021 Symposium on VLSI Circuits
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Dai Li
PhD 2021, now at Google
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Yan He
Ph.D. Student (started in 2018)
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Akhil Pakala
Ph.D. Student (started in 2020)
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Kaiyuan Yang
Assistant Professor of ECE